Homogeneous multiprocessing and the future of silicon design paradigms

This paper addresses two challenges of the consumer semiconductor industry: (1) economical and social forces are increasingly reducing the length of product life cycles, and (2) the continuing exponential growth of the on-chip transistor count is pushing design complexity. In concert these two trends represent a formidable challenge for semiconductor companies that aim to benefit from future technological developments in highly competitive markets. The paper derives a relation between on-chip memory real estate and compute logic, suggesting that homogeneous multiprocessors are an unavoidable consequence of the technology curve. A particular approach to homogeneous multiprocessing is then presented that combines scalability with high computational performance and with high power efficiency. We also present the implementation of a programming paradigm for homogeneous multiprocessors that focuses on reuse of tested and approved functions at the software level. This enables a shift from today's not-so-successful practice of hardware core reuse to the reuse of functions that have very well defined and uniform interfaces. The time frame for large scale commercial application of this type of homogeneous multiprocessor architecture is expected to coincide with the arrival of 0.07 micron technology for consumer products, i.e. 2006 and beyond. The paper concludes with a case study of an MPEG2 decoder and how a few simple guidelines can significantly increase the exposed concurrency of the application.