Maximizing functional test coverage in ASICs using evolutionary algorithms

This paper describes a prototype test bench used at the Intel Corporation's Oregon Design Center to functionally test ASICs. The test bench uses an evolutionary algorithm, but a direct approach is not used-i.e., the evolutionary algorithm does not explicity evolve the test patterns. Instead, an indirect approach is used where the evolutionary algorithm evolves a set of control parameters, and it is these parameters that the test bench uses to create the test pattern set. Preliminary test results from a moderate size ASIC are presented to show the effectiveness of our method.