A 6.25 ns random access 0.25 /spl mu/m embedded DRAM

A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.