An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme

An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.