Impact analysis of process variability on digital circuits with performance limited yield

In this paper we present a framework for the statistical design analysis of large logic circuits. It allows one to accurately predict and analyze the impact of process variations on relevant circuit performance parameters, such as critical path delay, clock skew and signal race conditions. The proposed statistical design analysis system is based on the efficient generation of linearized models for the stage delay sensitivities to Front End Of Line (FEOL) and Back End Of Line (BEOL) process parameter variations. By using a set of intermediate RSM representations, the actual underlying FEOL/BEOL process parameters are mapped into an auxiliary set of macro-parameters, such as NMOS and PMOS I/sub DSS/ and V/sub TH/, which can be more easily observed and controlled by process and device engineers. In this way the linearized performance models can be applied to generate product speed-yield maps as functions of the above set of controllable and observable macro-parameters, which can be finally used to center the process and optimize product yield.