Run-time reconfiguration: towards reducing the density requirements of FPGAs

This paper presents an approach to increase the functional density of programmable logic devices (PLDs) using a programming technique called run-time reconfiguration (RTR) and the sequencing of time exclusive PLD configurations. The fundamental requirement permitting a design to increase the effective functional density of a PLD using RTR is the ability to decompose the design functionally into time exclusive stages, where each stage is synthesized as a separate PLD configuration. These distinct PLD configurations are then sequenced optimally through the device during the run-time. The distinctive feature of this approach is an increase in the effective functional density of a PLD as compared to a single-configured implementation since the effective functional density in such an RTR system is proportional to the sum of all distinct PLD configurations.