Efficient implementation of the discrete wavelet transform on the parallel DSP-RAM architecture

Applications of the wavelet transform have increased significantly in the last decade. As a result, the VLSI implementation of the discrete wavelet transform has become very important for real time operations. In this paper, we propose an efficient implementation of the wavelet transform based on the pyramid algorithm. The proposed implementation employs a programmable, massively-parallel hardware architecture known as the DSP-RAM. Preliminary investigation shows that the proposed architecture can be adapted to efficiently support the pyramid algorithm.