A VLSI implementation of an adaptive-effort low-power Viterbi decoder for wireless communications

Low-power error-correction is required for 3rd generation digital wireless devices. Adaptive-reduced state sequence detection (A-RSSD) modifies a Viterbi decoder to use far less computational effort than is typical. RSSD neglects the oldest p bits of the encoder's state machine, treating the code as if it were of length K/spl acute/=K-p. Through successive reduction of p, decoding can proceed with more effort until a frame is correctly decoded. This paper describes the only known VLSI implementation of A-RSSD. The presented architecture is an adaptive strength, state-parallel, bit-serial structure. It features soft-decision, continuous stream traceback decoding, with K' ranging from 3 to 11. As such it employs between 4 and 1024 ACS units. The branch metric computer and ACS units are mostly conventional, while special consideration must be given to branch label generation, sub-state estimation, and ACS interconnection structure. Other low-power techniques are also applied, specifically with respect to clock gating, and traceback RAM structure. Design tradeoffs are discussed, and performance estimates are presented.