Fault-tolerance of associative memories based on neural networks

The authors discuss the hardware fault tolerance of associative memories. They study device parameter variations across a chip, which affect essentially the characteristics of analog circuits used by several architectures. The effects of these errors on the performance are examined by means of three typical representatives: the Hopfield model, the self-organizing feature map, and the Boltzmann machine. The authors present a worst-case estimation of the guaranteed fault tolerance of these networks and discuss the consequences for the features of the associative memories. The main result is that the fault tolerance decreases with the number of weights but can be improved by using spare codes or self-organization in connection with added resources.<
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