Effect of RTL coding style on testability

This paper illustrates the effect of functional Register Transfer-Level (RTL) coding styles on the testability of synthesized gate-level circuits. Thus, the advantage of having an RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testability reduces the total silicon area of the gate-level circuit as well. Experimental results presented in this paper demonstrate the benefits of having a proposed RTL code analyzer.