A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation

A 8-bit A/D converter using an efficient architecture is described. An important feature of this is a background offset cancellation scheme. This A/D converter has been implemented in a 0.18 /spl mu/m digital CMOS technology. It operates at up to 165 MS/s with an SNDR of 43.5 dB, a DNL of 0.7 LSB and an INL of 1 LSB. It occupies an active area of 0.9 mm/sup 2/ and has a power dissipation of 140 mW.