Design techniques for very low power ADCs

The three low-power ADC techniques of interleaving-by-4 with an amplifier reset and master sampling clock, using self-regulating CMOS push-pull amplifiers, and a hybrid comparator are described. They are demonstrated in an 8-bit 100 MSPS ADC which achieves +/- 0.25 LSB DNL and 7.5 effective bits with very low power, 54 mW at 2.7 V supply. The same 8-bit ADC, if optimized for 200 MSPS operation at 2.7 V, obtains a DNL below 0.4 LSB, and 7.3 (7.1) effective bits for a 10 MHz (100 MHz) input while consuming just 182 mW.