Characterization of parasitic behaviors in CMOS microsensors

In this paper some theoretical and experimental results are reported that refer to the study of parasitic phenomena in CMOS microsensors. In particular thermal and capacitive unwanted effects that arise during the characterization of some devices, realized by using standard microelectronics technologies and compatible micromachining strategies, are addressed. The choice of using standard technologies for developing microsystems is of great importance for its large intrinsic potentiality, in fact it opens very interesting scenarios for what regards batch production and reusable technologies. The results proposed allow for taking into account some other considerations for optimal results when designing novel structures based on the same technology.