Test chip for electrical linewidth of copper-interconnect features and related parameters

This paper reports a new electrical test structure for measuring the barrier-layer thickness and total physical linewidth of copper-cored interconnect features. The test structure has four critical dimension (CD) reference segments of different drawn linewidths. A new linewidth-extraction algorithm has been developed and extensively tested with
and sheet-resistance measurement emulations. It has also been applied to measurements extracted from scaled-up physical structures. A second test structure for measuring conducting feature and interlayer-dielectric (ILD) thickness by use of the charge-based capacitance method (CBCM) is located on the test chip. Test-chips featuring both of these structures have been patterned in aluminum using a standard 0.18 /spl mu/m CMOS process and preliminary results are reported here.