Design and FPGA implementation of orthonormal inverse discrete wavelet transforms

FPGA technology offers the potential for low cost and high performance for certain applications, including signal and image processing. Although the programming model which FPGA typically present to application developers is prohibitively low level, they are good target devices for rapid prototyping. The purpose of this paper is to present a novel bit-serial structure dedicated to inverse discrete wavelet transforms based on time-interleaved FIR filters. To overcome the problem of wait cycles within the structure, a second line of bit adders is provided. This allows the structure to use additional "dummy" cycles to deal with additional bits. The proposed structure is modular and scalable, which allows a bit-level parameterisation. To assess the effectiveness of the approach the design has been implemented efficiently on the Xilinx 4000 series FPGA.