The design of a one megabit non-volatile M-R memory chip using 1.5*5 mu m cells

A 10/sup 6/-bit chip has been designed using 1.5- mu m magnetoresistive double-layer memory elements and bipolar circuitry. The bipolar circuitry is based on nominal 1.25- mu m optical lithography. The total chip area of the design is 8.5 mm*9.5 mm. To enhance the signal-to-noise ratio, multiple reads are used with the nondestructive readout cells. Design read time is 3 mu s. Design write time is 0.2 mu s. The design includes three redundant, fuse-selectable sense lines for each group of 32 sense lines. If the bit failure rate is 0.0005 or less, yield loss for the 10/sup 6/-bit chip due to sense line failure is less than 19%. With improved lithography, elements as small as 0.75 mu m*2.5 mu m could be made from the material.<
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