A novel architecture for low-power design of parallel multipliers

In this paper, a new architecture for low-power design of parallel multipliers is proposed. Reduction of power consumption is achieved by reducing the circuit activity at the architecture level by dividing the multiplication circuit into clusters of smaller multipliers. By applying clock gating techniques and preprocessing operations on the input pattern using simple logic functions, some of these clusters that are producing a zero result can be disabled and hence saving the switching power component that could be consumed by these clusters. The amount of power savings is dependent on the nature of the input pattern, which varies according to the application. Analysis of the input pattern is performed. For testing purposes, A 8-bit multiplier prototype is constructed in 0.35 micron double metal CMOS technology using Cadence development tools. For the average case when all the input combinations have an equal probability of occurrence, HSPICE simulation results at 3.3 V and 500 MHz frequency show that the proposed architecture results in 13.4% power savings.