A multi-PLL clock distribution architecture for gigascale integration

This paper proposes a new semi-distributed architecture for clock distribution that is suitable for gigascale integration. First, the limitations associated with conventional clock distribution networks are discussed. Next, some of the alternative solutions to the clock distribution problem are reviewed and compared in terms of architecture, power dissipation, clock inaccuracy, and ease of implementation. The compatibility of the alternatives with established design-for-testability and design-for-debuggability techniques is also evaluated. Then, the proposed architecture is introduced. It employs an array of phase-locked loops (PLLs) synchronized using digital feedback. The new architecture addresses the limitations associated with conventional clocking networks, but does not suffer from the practical shortcomings affecting the alternatives proposed so far.