VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation

In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 /spl mu/ CMOS technology. The chip can achieve an encryption rate of 288 Mb/a and consume 32.7 mW while operating at a 72 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.