Automatic clock tree design with IPs in the system

A clock distribution methodology is presented for realizing the prespecified clock arriving time often occurring in the reusable block based design environment. In this strategy, not only the planar clock routing and buffer insertion are carried out simultaneously to minimize the total wire length and the clock skew, a full waveform simulation is used to ensure the signal integrity necessary for high-speed VLSI. Our experimental results demonstrate that the proposed method achieves a good circuit performance.