A statistical methodology for the design of high-performance current steering DAC's

Random device variations are a key factor limiting the performances of high-resolution CMOS current steering D/A converters. In this paper a novel design methodology based on statistical modeling of MOS drain current has been developed. This technique requires firstly an estimation of mean value and autocorrelation function of a single stochastic process, which all the process/device variations are lumped in. Then a behavioral model of D/A converters has been developed. Finally, the statistical simulation of static performances (DNL and INL) has been carried out for different DAC architectures.