Design trade-off in merged DRAM logic for video signal processing

The trade-off in designing merged DRAM logic (MDL) is explored for video signal processing. Computing requirements and memory bandwidths are quantitatively analyzed in the programmable MDL architecture. The number of processing elements (NPE) and the number of bus width (NBW) are obtained as a function of macro block rate, clock frequency, data rate, and number of clock/memory access cycles. Optimal MDL design parameters are determined from the minimum cost and design metrics: DRAM access rate (DAR) and area ratio of DRAM (ARD).