Low-power motion-estimation architecture based on a novel early-jump-out technique

This paper presents an architectural enhancement to reduce the power consumption of the block-matching motion estimation. Our approach is based on a novel early-jump-out technique for the computation of block-matching error. Augmenting it to the conventional systolic-architecture based VLSI engine drastically eliminates unnecessary computations. A rough estimate based on the simulation results at the algorithm level shows that, our enhanced architecture consumes 40% as much power as the conventional systolic array, while preserving the same throughput and a similar image quality.