ST: PERL package for simulation and test environment

We propose a simulation and test environment called Perl package for Simulation and Test (ST). ST provides an environment to describe unified testbenches for various simulation levels. ST also supports LSI testers. ST is implemented as a Perl package. You can write your testbench according to the Perl syntax. ST supports simulators such as Verilog or SPICE. Expected vectors can be compared with simulated results during Verilog simulation. Bi-directional ports can be handled on SPICE.