An entropy-based algorithm to reduce area overhead for bipartition-codec architecture

Bipartition-codec scheme has been used as one of the effective power reduction techniques in logic-level circuit design. It treats each output value of a combinational circuit as one state of an FSM, and extracts the most actively transitive states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, the encoding technique is used to encode the highly active subcircuit for further power reduction. Although we can get a large amount of power reduction in the previous proposed bipartition algorithm, the area overhead is considerably large. In this paper, we propose an effective heuristic algorithm based on entropy, which offers a theoretical area model to resolve the area overhead problem in the bipartition-codec architecture. The experimental results show that the area can be averagely reduced by 16% with 1.8% marginal power increase compared to the previous proposed probabilistic-driven algorithm.