A single-amplifier 6-bit CMOS pipeline A/D converter for WCDMA receivers

An embedded single-amplifier 6-bit 15.36 MS/s CMOS pipeline A/D converter for WCDMA receivers is presented. By sharing an operational amplifier with two sequential stages and by using a mismatch insensitive dynamic comparator a total power dissipation of only 12 mW from 2.7 V supply is achieved. Special emphasis is put on the reduction of substrate noise coupling from the ADC's to the low noise amplifier and a very good isolation is achieved. The ADC's are implemented in a 0.35-/spl mu/m BiCMOS technology using only CMOS transistors and occupying 0.45 mm/sup 2/. According to the measurements, a DNL and INL of 0.27 LSB and 0.18 LSB are achieved while the SFDR and SNDR are 50 dB and 36 dB, respectively.