Design of DDFS-driven PLL frequency synthesizer with reduced complexity

DDFS-driven PLL synthesizer has a high frequency resolution and wide frequency bandwidth. Since the output of DDFS is a synthesized analog signal, a waveform shaper is needed to provide the digital input for a DDFS-driven PLL synthesizer using the digital type phase detector. Furthermore, a lot of components in a DDFS unit can increase the switching time and the power consumption. In this paper, we propose a new design method of a DDFS-driven PLL synthesizer, which does not need the waveform shaper as well as the extra circuits of DDFS. As a result, the proposed method makes improvements to such quality factors as switching time and power consumption, compared with the conventional DDFS-driven PLL frequency synthesizer.