60 Gbps throughput demonstration of an asynchronous SFQ-pulse arbitration circuit

We demonstrated the experimental operation of a single flux quantum (SFQ) pulse arbitration circuit for rapid single flux quantum (RSFQ) digital applications. The circuit arbitrates two asynchronous incoming signals with the internal clock signal, and produces two signals with a time difference. The circuit consists of two data latches and a clock generator based on a ring oscillator. We fabricated the circuit using NEC's 2-/spl mu/m standard fabrication technology, and tested it in two ways. Firstly we tested throughput characteristics. From measurements of the average voltage of output Josephson Junctions, we confirmed that the throughput was indeed controlled by the clock signal up to around 60-GHz. Secondly we tested the arbitration function. The test used a new testing circuit connected with output side of the arbitration circuit. This circuit consists of a confluence buffer, a splitter and three SFQ/DCs, and was capable of monitoring output signals and their arrival time difference. We changed the difference in arrival times of the input signals to the arbiter circuit, and observed two output signals with the test circuit. The observed signals show that they always sent out with time difference, and we thus confirmed the correct operation of the circuit even for pairs of input signals with the same arrival time.