CMOS compatible HV gate-shifted LDD-NMOS

This brief presents an improvement of lightly doped drain (LDD) FET based on a drain engineering technique-the gate-shifting. Gate-shifted LDD (GSLDD) devices were fabricated in a submicron CMOS technology with no extra processing steps. Breakdown voltages in the range of 50 V and specific ON-resistances in the range of 2-4 m/spl Omega//spl middot/cm/sup 2/ were attained.