Software phase-locked loop applied to dynamic voltage restorer (DVR)

In this paper, the analytical and practical design issues of a software phase-locked loop (SPLL) for DVR are presented. A SPLL model that uses a lag/lead loop controller, is derived in order to analyse the system performance and filtering characteristic by the use of bode diagrams and root-locus methods. In DVR applications, parameters of the design of the SPLL controller are not only dependent on the steady state and dynamic state, but also on practical conditions such as utility unbalance, voltage sag/swell magnitude, voltage harmonics, phase jumps and frequency variations. Therefore, the practical aspect of the SPLL implementation has also been discussed. Experimental results demonstrate its phase tracking capability.