Scaling-induced reductions in CMOS reliability margins and the escalating need for increased design-in reliability efforts

Scaling, for enhanced performance and cost reduction reasons, has pushed existing CMOS materials much closer to their intrinsic reliability limits. Future robust designs will require a strong team effort whereby the design engineer must clearly understand the process variability and its impact on reliability. This strong team effort, between design and process, will become critically important as the industry is seeking to replace the very materials that has made the industry so successful: Si substrates, SiO/sub 2/ gate-dielectric, Al-based metallization and SiO/sub 2/ interconnect-dielectrics.