A low jitter, fast locking delay locked loop using measure and control scheme

The proposed measure and control scheme enables the DLL to lock on to the reference clock within 2 cycles which is comparable to SMD (Synchronous Mirror Delay) type DLL and maintains the locked state with the aid of closed loop control, which is a feature of register controlled DLL. In addition, in order for the delay control loop to have fine delay resolution, the unit delay, which is an inverter delay, is sliced to smaller fine delays by a phase blender. This proposed structure has the two inconsistent features of jitter and locking time at the same time. The proposed scheme is fabricated in 0.6um CMOS process and shows 16 [ps] rms jitter and 2 cycles locking time, and consumes 120 mW including I/O circuit.