Generation of accurate on-chip time constants and stable transconductances

A method for generating accurately known on-chip time constants and less accurate but stable transistor transconductances over process, power-supply, and temperature variations is presented. The technique uses a constant-g/sub m/ bias circuit, which has a resistor that is tuned with a fully integrated CMOS phase-locked loop (PLL) locked to an external frequency reference (normally present in most systems). Other on-chip analog circuits biased using the same constant-g/sub m/ bias circuit are also stabilized. The PLL uses a charge-pump structure with three control loops (two digital and one analog) having overlapping ranges with hysteresis to minimize tuning glitches in the steady state. The PLL has a lock range of 135 to 300 MHz, and displays an RMS jitter of 15.6 ps. The transconductances generated from the circuit display a 2.2% variation for a 60/spl deg/C change in temperature, and a 1.3% variation for a 10% variation in power-supply voltage. The design has been fabricated in a 0.35-/spl mu/m CMOS process, using an active area of 1200/spl times/1200 /spl mu/m/sup 2/ and draws 5.8 mA from a 3.3-V supply.