Design and emulation of 4/spl times/4 ATM integrated switching unit

For an ATM switching unit the buffering and queuing of cells are a key problem. In this paper A hierarchic 4/spl times/4 integrated ATM switching unit is designed and emulated on Xilinx Foundation Software. In the design the technique of combining the state dependent principle and the cyclic principle is adopted. For cell queuing the state dependent principle is a first priority, and the cyclic principle is applied if the buffers are in the same status. The explicit forward congestion notification is adopted in traffic control.