Hardware implementation of packet-fair queuing schedulers in high speed networks

Recently much research attention has been focused on implementing efficient per-flow scheduling mechanism in next generation ATM switches and routers to support the high speed multiplexing of a large number of flows with diverse traffic parameters and QoS requirements over the same network link. In this paper, we present an efficient FPGA design of packet-fair queuing schedulers based on discrete backlogged rates and packet lengths. According to the results of timing simulation, this design can process IP packets at 1.2 Gb/s which is fully capable of supporting two OC-12 POS media interfaces in high speed routers.