Circuit theory and interconnect analysis for DSM chip design

Summary form only given. With deep submicron (DSM) ICs, it is known that interconnect introduces critical problems on signal integrity for chip design. Interconnect delay dominates the gate delay. Other problems are the IR drop and crosstalk. As we reach frequencies approaching one gigahertz, it is necessary to model the interconnect as transmission lines. Clearly, new models for interconnect are necessary for analysis and design. The SPICE simulator is no longer adequate because of its limitation in speed and the size of the circuit. During the past ten years, researchers have begun to take a fresh look at circuit simulation for DSM chip design.