Post-layout transistor sizing for power reduction in cell-based design

We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using five circuits. The power dissipation is reduced by 77% maximum and 65% on average without delay increase.