Formal verification of pulse-mode asynchronous circuits

This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existing technique for verifying asynchronous circuits under relative timing constraints at several levels of abstraction.