A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

In this paper, a high-speed PLA based on latch sense amplifiers and a charge sharing scheme is presented. The circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By latch sense amplifiers, a read-out scheme sensing the differential voltage of dual-rail bit-lines caused by charge sharing is used for high-speed operation. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-/spl mu/m double-poly, triple-metal CMOS process. Results of HSPICE simulation are 2.9 times faster than the conventional CMOS circuit. The measured results show a good agreement with the simulation.