A high-performance switch with applications to frame relay networks

A design is proposed for an n*n switch to be used in frame relay networks. The design is based on a single storage unit for packets and hardware-based mechanism for handling simultaneously arriving packets over different input channels which may be intended for the same output channel. The switch is flexible in that it can handle variable length packets, a large number of input/output channels, and a wide range of channel speeds. It can perform cut-through switching and thus decrease packet delay through the network. It allows the design of high-throughput frame-relay nodes, simplifying the design and management of large networks. Its use of a hardware-implemented dynamic scheme for allocating storage allows efficient utilization of buffer space.<
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