Low-power CMOS implantable nerve signal analog processing circuit

We describe a low-voltage low-power CMOS nerve signal analog processing circuit for biomedical applications. It is dedicated to an implantable bladder controller. After amplifying the nerve signal with low-noise high-CMRR instrumentation amplifier, it is rectified and bin-integrated (RBI) with a low-power CMOS analog processing circuit. This circuit is based on switched capacitor technique. Using techniques to reduce operational amplifier requirements ensures low-power consumption. The circuit has been designed in CMOS 0.35 /spl mu/m technology. The simulation results of the main parts of the proposed analog circuit are presented. At a supply voltage of 2.2 V the power dissipation is 700 /spl mu/W.