Circuit design for a 2.2 GB/s memory interface

A 2.2 GB/s signaling interface for main memory uses a DLL that allows for in-system timing calibration with 1.4/spl deg/ resolution, and output drivers with limited positive feedback to increase voltage margin. In a 0.25 /spl mu/m CMOS process, the prototype chips operate to 2.6 GB/s.