Comparison of two standard WLR current-ramped tests for oxide reliability

A comparison between the GOX-Reliability results obtained on 7.5 nm and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms-a CSQ (Current Step Qbd) stress on the one hand and the JEDEC J-Ramp, on the other hand-are presented. The observed influence of the ramping profile and the step holding time t/sub step/ on the reliability data shows a strong dependence on the type of device under test (DUT). The P-type MOS-devices seem to be more susceptible to the changes of the current ramping rate. The obtained results are discussed in terms of the GOX interface roughness, depletion effects during the stress, and the serial resistance of the test structure.