A probabilistic-physics-of-failure/short-time-test approach to reliability assurance for high-performance chips: models for deep-submicron transistors and optical interconnects

This paper deviates from strictly empirical chip reliability approaches and uses instead a chip reliability methodology based on probabilistic-physics-of-failure (PPoF) principles. We derive the failure-time distribution of both deep-submicron transistors and optical interconnects owing to the presence of a common defect activation energy distribution. We show how short-time device degradation can be used to extract the tails of the semi-symmetric failure-time distribution (important for long-term reliability qualification). Applying novel reliability qualification rules based on this failure-time distribution, "latent failures" can then be avoided through design changes for reliability.