Fast-bit-limited lifetime modeling of advanced floating gate non-volatile memories

The few fast bits, resulting from stress induced leakage current, that are found in a memory array limit lifetime of an entire device. Instead of classical temperature accelerated tests, 'simple' gate stress represents therefore the correct method to study the advanced non-volatile memory retention behavior. In this paper a model is proposed to predict the memory lifetime under use conditions based on accelerated gate stress measurements. The model considers a statistical approach, in order to overcome the erratic behavior of fast bits. It enables predicting the lifetime of memory products as function of memory size and number of write/erase cycles. Application of the model is discussed as well as a wafer level implementation form.