On the methodology of assessing hot-carrier reliability of analog circuits

An integrated methodology for assessing analog hot-carrier reliability is proposed. Taking advantage of the unique requirements of analog circuits as well as the well-developed circuit analysis techniques, the methodology focuses on the characterization and modeling of /spl Delta/V/sub T/ and /spl Delta//spl mu/ (as a function of hot-carrier degradation) at the device level and seeks to model circuit-level DC performance parameters degradation through analytical expressions derived from SPICE Model 1.