On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning

We show experimentally that the number of clustering levels in a multilevel circuit partitioning algorithm may be reduced if guided by a measure of regularity applied to the input circuit netlist. Furthermore, we devise a simple tactic to reduce the number of runs in a multistart circuit partitioning algorithm. As a consequence CPU-time is saved. This comes at only a minor degradation in solution cost. Experiments were performed by applying our algorithm ML/sub AF/ to the ISPD-98 benchmarks.