Fast computations on a low-cost DSP-based shared-memory multiprocessor system

Typical DSP algorithms require more memory bandwidth. Thus unibus shared-memory systems can support only a handful of processors. The proposed architecture can effectively support 64 digital signal processors (DSPs) in contrast to a maximum of 4 DSPs supported by existing bus-interconnected systems. This significant enhancement is achieved by introducing two small programmable fast memories (Twins) between the processor and the shared bus interconnect. While one memory is transferring data from/to the shared memory, the other is supplying the core processor with data. The proposed architecture eliminates the traditional direct linkage of the shared-bus and processor data bus; thus making feasible the utilization of a wider shared bus. Simulation results show that: the fast prefetching memories and the wider shared bus provide additional bus bandwidth to the system, which eliminates large memory latencies; such memory latencies constitute the major drawback for the performance of shared-memory multiprocessors.