A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme

A 20-bit delta-sigma A/D converter is implemented in a 0.6-/spl mu/m CMOS process with a single 5-V supply. It provides a 25-kHz data rate for high-speed dc measurement while maintaining good the performance required for accurate dc measurement such as noise, linearity and drift. The front-end programmable gain amplifier (PGA) allows the user to optimize their system for different input ranges. Offset and finite gain compensation are used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta-sigma converter section, low frequency error reduction is achieved through the use of chopper stabilization technique. A frequency-shaped chopper stabilization scheme is used to alleviate the intermodulation tone problem commonly associated with the use of the fixed rate chopping in delta-sigma modulators. This A/D converter achieves 2.5 ppm RMS noise and 12 ppm INL at gain of one.