CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high d
v
/d
t
of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the d
v
/d
t
with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the d
v
/d
t
sequence of the switching transients. Hence, the d
v
/d
t
and d
i
/d
t
can be actively controlled separately, and the tradeoff between the d
v
/d
t
and
E
_ON
switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for d
v
/d
t
active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak d
v
/d
t
from –175 to –120 V/ns for the 400 V application.